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single, 3 v, cmos, lvds differential line receiver ADN4662 rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2009 analog devices, inc. all rights reserved. features 15 kv esd protection on input pins 400 mbps (200 mhz) switching rates flow-through pinout simplifies pcb layout 2.5 ns maximum propagation delay 3.3 v power supply high impedance outputs on power-down low power design: typically 3 mw (quiescent) interoperable with existing 5 v lvds drivers accepts small swing (310 mv typical) differential signal levels supports open, short, and terminated input fail-safe 0 v to ?100 mv threshold region conforms to tia/eia-644 lvds standard industrial operating temperature range: ?40c to +85c available in surface-mount (soic) package applications point-to-point data transmission multidrop buses clock distribution networks backplane receivers functional block diagram r out r in+ r in? v cc ADN4662 gnd nc nc nc 07960-001 figure 1. general description the ADN4662 is a single, cmos, low voltage differential signaling (lvds) line receiver offering data rates of over 400 mbps (200 mhz), and ultralow power consumption. it features a flow-through pinout for easy pcb layout and separation of input and output signals. the device accepts low voltage (310 mv typical) differential input signals and converts them to a single-ended 3 v ttl/ cmos logic level. the ADN4662 and its companion driver, the adn4661, offer a new solution to high speed, point-to-point data transmission, and a low power alternative to emitter-coupled logic (ecl) or positive emitter-coupled logic (pecl).
ADN4662 rev. 0 | page 2 of 12 table of contents features .............................................................................................. 1 ? applications ....................................................................................... 1 ? functional block diagram .............................................................. 1 ? general description ......................................................................... 1 ? revision history ............................................................................... 2 ? specifications ..................................................................................... 3 ? ac characteristics ........................................................................ 4 ? absolute maximum ratings ............................................................ 6 ? esd caution...................................................................................6 ? pin configuration and function descriptions ..............................7 ? typical performance characteristics ..............................................8 ? theory of operation ...................................................................... 11 ? applications information .......................................................... 11 ? outline dimensions ....................................................................... 12 ? ordering guide .......................................................................... 12 ? revision history 1/09revision 0: initial version
ADN4662 rev. 0 | page 3 of 12 specifications v dd = 3.0 v to 3.6 v; c l = 15 pf to gnd; all specifications t min to t max , unless otherwise noted. table 1. parameter 1 symbol min typ 2 max unit conditions/comments lvds input high threshold at r in+, r in? 3 v th +100 mv v cm = 1.2 v, 0.05 v, 2.95 v low threshold at r in+ , r in? 3 v tl ?100 mv v cm = 1.2 v, 0.05 v, 2.95 v input current at r in+ , r in? i in ?10 1 +10 a v in = 2.8 v, v cc = 3.6 v or 0 v ?10 1 +10 a v in = 0 v, v cc = 3.6 v or 0 v ?20 1 +20 a v in = 3.6 v, v cc = 0 v output output high voltage v oh 2.7 3.1 v i oh = ?0.4 ma, v id = +200 mv 2.7 3.1 v i oh = ?0.4 ma, input terminated 2.7 3.1 v i oh = ?0.4 ma, input shorted output low voltage v ol 0.3 0.5 v i ol = 2 ma, v id = ?200 mv output short-circuit current 4 i os ?15 ?47 ?100 ma enabled, v out = 0 v input clamp voltage v cl ?1.5 ?0.8 v i cl = ?18 ma power supply no load supply current i cc 5.4 9 ma inputs open esd protection r in+ , r in? pins 15 kv human body model all pins except r in+ , r in? 4 kv human body model 1 current into device pins is defined as positive. current out of device pins is defined as negative. all voltages are reference d to ground, unless otherwise specified. 2 all typicals are given for: v cc = +3.3 v, t a = 25c. 3 v cc is always higher than r in+ and r in? voltage. r in? and r in+ are allowed to have a voltage range of ?0.2 v to v cc ? v id /2. however, to be compl iant with ac specifications, the common voltage range is 0.1 v to 2.3 v. 4 output short-circuit current (i os ) is specified as magnitude only; the minus sign indicates direction only. only one output should be shorted at a time. do not exceed maximum junction temperature specification.
ADN4662 rev. 0 | page 4 of 12 ac characteristics v dd = 3.0 v to 3.6 v; c l 1 = 15 pf to gnd; all specifications t min to t max , unless otherwise noted. table 2. parameter symbol min typ 2 max unit conditions/comments 3 differential propagation delay high to low t phld 1.0 2.15 2.5 ns c l = 15 pf, v id = 200 mv (see figure 2 and figure 3 ) differential propagation delay low to high t plhd 1.0 2.03 2.5 ns c l = 15 pf, v id = 200 mv (see figure 2 and figure 3 ) differential pulse skew |t phld ? t plhd | 4 t skd1 0 80 400 ps c l = 15 pf, v id = 200 mv (see figure 2 and figure 3 ) differential part-to-part skew 5 t skd3 1.0 ns c l = 15 pf, v id = 200 mv (see figure 2 and figure 3 ) differential part-to-part skew 6 t skd4 1.5 ns c l = 15 pf, v id = 200 mv (see figure 2 and figure 3 ) rise time t tlh 510 800 ps c l = 15 pf, v id = 200 mv (see figure 2 and figure 3 ) fall time t thl 445 800 ps c l = 15 pf, v id = 200 mv (see figure 2 and figure 3 ) maximum operating frequency 7 f max 200 250 mhz all channels switching 1 c l includes probe and jig capacitance. 2 all typicals are given for v cc = 3.3 v, t a = 25c. 3 generator waveform for all tests unless otherwise specified: f = 1 mhz, z o = 50 , t tlh and t thl (0% to 100%) 3 ns for r in+ /r in? . 4 t skd1 is the magnitude difference in differential propagation delay time between the positive going edge and the negative going edge of the same channel. 5 t skd3 , part-to-part skew, is the differential channel-to-channel skew of any event between devices. this specification applies to de vices at the same v cc and within 5c of each other within the operating temperature range. 6 t skd4 , part-to-part skew, is the differential channel-to-channel skew of any event between devices. this specification applies to de vices over recommended operating temperature and voltage ranges, and across process distribution. t skd4 is defined as |maximum ? minimum| differential propagation delay. 7 f max generator input conditions: f = 200 mhz, t tlh = t thl < 1 ns (0% to 100%), 50% duty cycle, differential (1. 05 v to 1.35 v peak-to-peak). ou tput criteria: 60%/40% duty cycle, v ol (maximum 0.4 v), v oh (minimum 2.7 v), load = 15 pf (stray plus probes).
ADN4662 rev. 0 | page 5 of 12 test circuits and timing diagrams v cc r out r in+ c l signal generator 50? 50? r in? c l = load and test jig capacitance 07960-002 figure 2. test circuit for receiver propagation delay and transition time 20% 80% 80% 20% 1.5v 1.5v t plhd t phld r in? r in+ 0v (differential) t tlh t thl v oh v ol 1.2v 1.3v 1.1v r out v id = 200mv 07960-003 figure 3. receiver propagation delay and transition time waveforms
ADN4662 rev. 0 | page 6 of 12 absolute maximum ratings t a = 25c, unless otherwise noted. table 3. parameter rating v cc to gnd ?0.3 v to +4 v input voltage (r in+ , r in? ) to gnd ?0.3 v to v cc + 3.9 v output voltage (r out ) to gnd ?0.3 v to v cc + 0.3 v operating temperature range industrial temperature range ?40c to +85c storage temperature range ?65c to +150c junction temperature (t j max) 150c power dissipation (t j max ? t a )/ ja soic package ja thermal impedance 149.5c/w reflow soldering peak temperature pb-free 260c 5c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution
ADN4662 rev. 0 | page 7 of 12 pin configuration and fu nction descriptions r in? 1 r 2 v cc 8 r 7 in+ nc 3 nc 4 out nc 6 gnd 5 nc = no connect ADN4662 top view (not to scale) 07960-004 figure 4. pin configuration table 4. pin function descriptions pin no. mnemonic description 1 r in? receiver channel 1 inverting input. when this input is more negative than r in+ , r out is high. when this input is more positive than r in+ , r out is low. 2 r in+ receiver channel 1 noninverting input. wh en this input is more positive than r in? , r out is high. when this input is more negative than r in? , r out is low. 3 nc no connect. 4 nc no connect. 5 gnd ground reference point for all circuitry on the part. 6 nc no connect. 7 r out receiver output (3 v ttl/cmos). if the differential input voltage between r in+ and r in? is positive, this output is high. if the differential input voltag e is negative, this output is low. 8 v cc power supply input. this part can be operated from 3.0 v to 3.6 v.
ADN4662 rev. 0 | page 8 of 12 typical performance characteristics 3.6 3.5 3.4 3.3 3.2 3.1 3.0 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 output high voltage, v oh (v) power supply voltage, v cc (v) i load = ?400a t a = 25c v id = 200mv 07960-007 figure 5. output high voltage vs. power supply voltage 33.60 33.55 33.50 33.45 33.40 33.35 33.30 33.25 3.0 3.1 3.2 3.3 3.4 3.5 3.6 output low voltage, v ol (mv) power supply voltage, v cc (v) i load = 2ma t a = 25c v id = ?200mv 07960-008 figure 6. output low voltage vs. power supply voltage ? 35 ?37 ?39 ?41 ?43 ?45 ?47 ?49 ?51 ?53 ?55 3.0 3.1 3.2 3.3 3.4 3.5 3.6 output short-circuit current, i os (ma) power supply voltage, v cc (v) 07960-009 v out = 0v t a = 25c figure 7. output short-circuit current vs. power supply voltage a = 25c 0 ?5 ?10 ?15 ?20 ?25 ?30 ?35 ?40 ?45 ?50 3.0 3.1 3.2 3.3 3.4 3.5 3.6 threshold voltage, v th (mv) power supply voltage, v cc (v) 07237-011 v out = 0v t a = 25c figure 8. threshold voltage vs. power supply voltage 0 5 10 15 20 25 30 35 40 45 50 0.01 0.1 1 10 100 1000 frequency (mhz) power supply current, i cc (ma) t a = 25c v cc = 3.3v v id = 200mv 07960-023 c l = 15pf figure 9. power supply current vs. frequency 0 1 2 3 4 5 6 7 8 9 10 ?40 ?15 10 35 60 85 ambient temperature (c) power supply current, i cc (ma) v cc = 3.3v v id = 200mv c l = 15pf frequency = 1mhz 07960-024 figure 10. power supply current vs. ambient temperature
ADN4662 rev. 0 | page 9 of 12 2.5 2.4 2.3 2.2 2.1 2.0 1.9 1.8 ?40 ?15 10 35 85 60 07960-014 ambient temperature, t a (c) differential propagation delay, t plhd , t phld (ns) t phld t plhd v cc = 3.3v v id = 200mv frequency = 200mhz c l = 15pf figure 11. differential propagation delay vs. ambient temperature 4.0 3.5 3.0 2.5 2.0 1.5 00.51.01.5 3 2.0 .0 2.5 07960-015 common-mode voltage, v cm (v) differential propagation delay, t plhd , t phld (ns) t phld t plhd t a = 25c v id = 200mv frequency = 200mhz c l = 15pf figure 12. differential propagation delay vs. common-mode voltage 2.30 2.25 2.20 2.15 2.10 2.05 2.00 1.95 1.90 1.85 3.0 3.1 3.2 3.3 3.6 3.4 3.5 07960-016 power supply voltage, v cc (v) differential propagation delay, t plhd , t phld (ns) t phld t plhd t a = 25c v id = 200mv frequency = 200mhz c l = 15pf figure 13. differential propagation delay vs. power supply voltage 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 0 0.5 1.0 1.5 2.0 2.5 3.0 differential input voltage, v id (v) differential propagation delay, t plhd , t phld (ps) t plhd t phld v cc = 3.3v c l = 15pf frequency = 200mhz v cm = 1.2v 0 7960-025 figure 14. differential propagation delay vs. differential input voltage 250 200 150 100 50 0 ?50 ?100 3.0 3.1 3.2 3.3 3.4 3.5 3.6 07960-018 differential skew, t skew (ps) power supply voltage, v cc (v) t a = 25c v id = 200mv frequency = 200mhz c l = 15pf figure 15. differential skew vs. power supply voltage 160 140 120 100 80 60 40 20 0 ?40 ?15 10 35 60 85 07960-019 differential skew, t skew (ps) ambient temperature, t a (c) v id = 200mv v cc = 3.3v frequency = 200mhz c l = 15pf figure 16. differential skew vs. ambient temperature
ADN4662 rev. 0 | page 10 of 12 600 560 580 540 520 500 480 460 440 420 400 3.0 3.1 3.2 3.3 3.6 3.4 3.5 07960-020 power supply voltage, v cc (v) transition time, t tlh , t thl (ps) t thl v cc = 3.3v v id = 200mv frequency = 25mhz c l = 15pf t tlh figure 17. transition time vs. power supply voltage 600 550 500 450 400 350 ?40 ?15 10 35 60 85 07960-021 ambient temperature, t a (c) transition time, t tlh , t thl (ps) t thl t tlh v cc = 3.3v v id = 200mv frequency = 200mhz c l = 15pf figure 18. transition time vs. ambient temperature 1.5 1.7 1.9 2.1 2.3 2.5 2.7 2.9 3.1 10 15 20 25 30 35 40 45 load (pf) differentialpropagationdelay, t plhd , t phld (ns) t plhd t phld t a = 25c v cc = 3.3v v id = 200mv frequency = 1mhz 07960-026 figure 19. differential propagation delay vs. load at 1 mhz 200 400 600 800 1000 1200 1400 1600 1800 10 15 20 25 30 35 40 45 load (pf) transition time, t tlh , t thl (ps) t tlh t thl t a = 25c v cc = 3.3v v id = 200mv frequency = 1mhz 07960-027 figure 20. transition time vs. load 1.5 1.7 1.9 2.1 2.3 2.5 2.7 2.9 10 15 20 25 30 35 40 45 load (pf) differentialpropagationdelay, t plhd , t phld (ns) t a = 25c v cc = 3.3v v id = 200mv frequency = 200mhz t plhd t phld 07960-028 figure 21. differential propagation delay vs. load at 200 mhz 0 200 400 600 800 1000 1200 1400 1600 1800 10 15 20 25 30 35 40 45 load (pf) transition time, t tlh , t thl (ps) t tlh t thl t a = 25c v cc = 3.3v v id = 200mv frequency = 200mhz 07960-029 figure 22. transition time vs. load at 200 mhz
ADN4662 rev. 0 | page 11 of 12 theory of operation the ADN4662 is a single line receiver for low voltage differential signaling. it takes a differential input signal of 310 mv typically and converts it into a single-ended 3 v ttl/cmos logic signal. a differential current input signal, received via a transmission medium, such as a twisted pair cable, develops a voltage across a terminating resistor, r t . this resistor is chosen to match the characteristic impedance of the medium, typically around 100 . the differential voltage is detected by the receiver and converted back into a single-ended logic signal. when the noninverting receiver input, r in+ , is positive with respect to the inverting input r in? (current flows through r t from r in+ to r in? ), then r out is high. when the noninverting receiver input r in+ is negative with respect to the inverting input r in? (current flows through r t from r in? to r in+ ), then r out is low. the ADN4662 differential line receiver is capable of receiving signals of 100 mv over a 1 v common-mode range centered around 1.2 v. this relates to the typical driver offset voltage value of 1.2 v. the signal originating from the driver is centered around 1.2 v and may shift 1 v around this center point. this 1 v shifting may be caused by a difference in the ground potential of the driver and receiver, the common-mode effect of coupled noise, or both. using the adn4663 as a driver, the received differential current is between 2.5 ma and 4.5 ma (typically 3.1 ma), developing between 250 mv and 450 mv across a 100 termination resis- tor. the received voltage is centered around the receiver offset of 1.2 v. in other words, the noninver ting receiver input is typically (1.2 v + [310 mv/2]) = 1.355 v, and the inverting receiver input (1.2 v ? [310 mv/2]) = 1.045 v for logic 1. for logic 0, the inverting and noninverting input voltages are reversed. note that because the differential voltage reverses polarity, the peak-to-peak voltage swing across r t is twice the differential voltage. current mode signalling offers considerable advantages over voltage mode signalling, such as rs-422. the operating current remains fairly constant with in creased switching frequency, whereas with voltage mode drivers the current increases exponentially in most cases. this is caused by the overlap as internal gates switch between high and low, which causes currents to flow from v cc to ground. a current mode device simply reverses a constant current between its two outputs, with no significant overlap currents. this is similar to emitter-coupled logic (ecl) and positive emitter- coupled logic (pecl), but without the high quiescent current of ecl and pecl. applications information figure 23 shows a typical application for point-to-point data transmission using the adn4663 as the driver. d in d out? r out r in? d out+ r in+ 100 ? r t 0.1f 10f tantalum 10f tantalum + + v cc 0.1f v cc gnd gnd adn4661 ADN4662 3.3 v 3.3 v 07960-119 figure 23. typical application circuit
ADN4662 rev. 0 | page 12 of 12 controlling dimensions are in millimeters; inch dimensions (in parentheses) are rounded-off millimeter equivalents for reference only and are not appropriate for use in design. compliant to jedec standards ms-012-a a 012407-a outline dimensions 0.25 (0.0098) 0.17 (0.0067) 1.27 (0.0500) 0.40 (0.0157) 0.50 (0.0196) 0.25 (0.0099) 45 8 0 1.75 (0.0688) 1.35 (0.0532) seating plane 0.25 (0.0098) 0.10 (0.0040) 4 1 85 5.00 (0.1968) 4.80 (0.1890) 4.00 (0.1574) 3.80 (0.1497) 1.27 (0.0500) bsc 6.20 (0.2441) 5.80 (0.2284) 0.51 (0.0201) 0.31 (0.0122) coplanarity 0.10 figure 24. 8-lead standard small outline package [soic_n] narrow body (r-8) dimensions shown in millimeters and (inches) ordering guide model temperature range package description package option ADN4662brz 1 ?40c to +85c 8-lead standard small outline package [soic_n] r-8 ADN4662brz-reel7 1 ?40c to +85c 8-lead standard small outline package [soic_n] r-8 1 z = rohs compliant part. ?2009 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d07960-0-1/09(0)

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